Single Bit and Multi-Bit Flash Memory Cells
Flash memory devices have been known for many years. In many “traditional” flash memory devices, each memory cell within a flash memory device stores one bit of information. Thus, the traditional way to store a bit in a flash memory cell has been by supporting two states of the memory cell. One state represents a logical “0” and the other state represents a logical “1”.
In a flash memory cell, the two states are implemented by having a floating gate situated above the cell's channel (the area connecting the source and drain elements of the cell's transistor), and having two valid states for the amount of charge stored within the floating gate. Typically, one state is with zero charge in the floating gate and is the unwritten state of the cell after being erased (commonly defined to represent the “I” state) and the other state is with some amount of negative charge in the floating gate (commonly defined to represent the “0” state). Having negative charge in the gate causes the threshold voltage of the cell's transistor (i.e. the voltage that has to be applied to the transistor's control gate in order to cause the transistor to conduct) to increase. It is possible to read the stored bit by checking the threshold voltage of the cell. If the threshold voltage is in the higher state then the bit value is “0” and if the threshold voltage is in the lower state then the bit value is “1”. Actually there is no need to accurately read the cell's threshold voltage. All that is needed is to correctly identify in which of the two states the cell is currently located. For this purpose it is sufficient to compare the threshold voltage of the cell to a reference voltage that is between the two states, and to determine if the cell's threshold voltage is below or above the reference value.
FIG. 1A (prior art) shows graphically how this works. Specifically, FIG. 1A shows a distribution of the threshold voltages of a large population of cells. Because the cells in a flash device are not exactly identical in their characteristics and behavior (due to, for example, small variations in impurity concentrations or defects in the silicon structure), applying the same programming operation to all of the cells does not cause all of the cells to have exactly the same threshold voltage. Instead, the threshold voltage is distributed as shown in FIG. 1A. Cells storing a value of “1” typically have a negative threshold voltage, such that most of the cells have a threshold voltage close to the central voltage value of the left peak (labeled 1) of FIG. 1A, with fewer cells having threshold voltages lower or higher than the central voltage of the left peak. Similarly, cells storing a value of “0” typically have a positive threshold voltage, such that most of the cells have a threshold voltage close to the central voltage of the right peak (labeled 0) of FIG. 1A, with fewer cells having threshold voltages lower or higher than the central voltage of the right peak.
In recent years, a new kind of flash device has appeared on the market, using “Multi Level Cells” (MLC). The term “Multi-Level Cell” is misleading because flash memory with a single bit per cell uses multiple i.e. two levels, as described above. Therefore, the term “Single Bit Cell” (SBC) is used hereinafter to refer to a memory cell of two levels and the term “Multi-Bit Cell” (MBC) is used hereinafter to refer to a memory cell of more than two levels, i.e. more than one bit per cell. The most common MBC flash memories at present are ones with two bits per cell, and therefore examples are given below using such MBC memories. It should however be understood that the present disclosure is equally applicable to flash memory devices that support more than two bits per cell. A single MBC cell storing two bits of information is in one of four different states. As the cell's “state” is represented by the cell's threshold voltage, an MBC cell supports four different valid ranges for the cell's threshold voltage. FIG. 1B (prior art) shows the threshold voltage distribution for a typical MBC cell of two bits per cell. As expected, FIG. 1B has four peaks, each peak corresponding to one state. As for the SBC, each state is actually a voltage range and not a single voltage. When reading the cell's contents, the cell's threshold voltage must be correctly identified in a definite voltage range. A cell designed for MBC operation e.g. in four states is typically operable as an SBC cell with two states. For example, it is known that MBC and SBC modes may co-exist within the same device. Thus, one may designate certain parts of the device to operate with highest density in MSC mode, while other parts are used in SDC mode to provide better performance.
MBC devices provide a significant cost advantage. An MSC device with two bits per cell requires about half the area of a silicon wafer than an SBC of similar capacity. However, there are drawbacks to using MBC flash. Average read and write times of MBC memories are longer than of SBC memories, resulting in worse performance. Also, the reliability of MSC is lower than SDC. The differences between the threshold voltage ranges in SMC are much smaller than in SBC. Thus, a disturbance in the threshold voltage (e.g. leakage of stored charge causing a threshold voltage drift or interference from operating neighboring cells) that are insignificant in SBC because of the large gap between the two states, may cause an SBC cell to move from one state to another, resulting in an erroneous bit. The end result is a lower performance specification of SAC cells in terms of data retention time or the endurance of the device to many write/erase cycles.
A First Discussion of Flash Pulse Parameters
The previous section related to MBC devices and “hybrid” devices including both multi-bit and single bit cells. The next three sections relate to both MBC devices, hybrid devices, and SBC-only devices.
FIGS. 1C and 1D illustrate the storage of a bit, either a zero bit or a one bit, in a cell of a flash memory. The examples of FIG. 1C-1D relate to SBC memories. For historical reasons, this process of storing data in a flash memory is called “programming” the flash memory. Nominally, a zero bit is represented by a cell threshold voltage V0 and a one bit is represented by a cell threshold voltage V1. Initially, the cell has a nominal threshold voltage V1. For example, after a block of a flash memory has been erased, all the cells have nominal threshold voltages V1. Because of unavoidable inaccuracies in the initializations of the cells, the actual threshold voltages are distributed around the nominal threshold voltage V1 according to a distribution curve 10. Then, to each cell that is to store a zero bit, a train 12 of programming voltage pulses 14 is applied, in order to inject electrons from the cell's silicon substrate through the cell's oxide layer into the cell's floating gate. Because the electrons move through the oxide layer by quantum mechanical tunneling or by hot injection, and because of non-uniformities in the cells' structures, the voltage required to inject enough electrons to increase the threshold voltage from V1 to V0 cannot be predicted accurately in advance. The voltage of the first pulse 14 is a starting voltage VS+ a programming voltage increment ? V. Every subsequent pulse 14 is higher than its predecessor by ? V. After each pulse 14 is applied, the cell is tested to see if its threshold voltage is sufficiently close to V0. If the threshold voltage is sufficiently close to V0 then the programming of cell is complete. Otherwise, the next pulse 14 is applied to the cell and the threshold voltage of the cell again is tested. Because the initial threshold voltages are distributed about the nominal voltage V1, and because of inaccuracies in the programming, the threshold voltages of the cells that store zero bits also are distributed about the nominal threshold voltage V0, according to a distribution curve 16.
Data are read from the flash memory cells by sensing the cells' threshold voltages. A threshold voltage greater than a transition threshold voltage VT halfway between V0 and V1 is interpreted as a zero bit. A threshold voltage less than VT is interpreted as a one bit. Over time, primarily because of the tunneling of electrons from the floating gates back to the substrate, the distributions 10 and 16 tend to become broader. The difference between threshold voltages V0 and V1 is selected to be great enough so that, over the lifetime of the flash memory, the likelihoods that the lower end 18 of distribution 16 will descend below VT and that the upper end 20 of distribution 10 will ascend above VT are negligible.
A Discussion of Flash Pulse Parameters and “Slow” vs. “Fast” Writing Modes
FIGS. 1E and 1F illustrate the programming of a zero bit in a cell of a flash memory according to a writing mode that is a “slow” writing mode relative to the writing mode illustrated in FIGS. 1C-1D. A train 22 of programming voltage pulses with a programming voltage increment twice as large as the programming voltage increment ? V of FIG. 1C is applied to the cell until the threshold voltage of the cell is sufficiently close to V0. The cell of FIGS. 1E and 1F is programmed in less time than the cell of FIGS. 1C and 1D. In some situations, this “speed benefit” may be obtained at the expense of the distribution 24 of the resulting threshold voltages around V0 being wider than distribution 16, which is shown in FIG. 1E in phantom for reference. Thus, the programming technique of FIGS. 1E-1F provides a relatively “fast” writing mode as compared to the relatively “slow” writing mode of FIGS. 1C-1D.
As noted above, average read and write times of MBC memories are longer than of SBC memories, resulting in worse performance. Thus, writing data to an SBC memory may provide a relatively “fast” writing mode compared to writing data to an MBC memory. Furthermore, writing data using the programming technique of FIGS. 1E-1F provides a relatively “fast” writing mode compared to writing data using the programming technique of FIGS. 1C-1D.
The skilled artisan will appreciate that these are just two examples, and that there are other ways in the art to obtain relatively “slow writing modes” and relatively “fast writing modes.” Furthermore, although the discussion of FIGS. 1C-1F related to the specific case of SBCs, it is appreciated that the principles described with reference to FIGS. 1C-1F are equally applicable to MBCs.
A Discussion of Flash Devices Coupled to Host Devices
FIG. 2A is a block diagram of an exemplary system including a host device 310 and a flash memory device 260. The host device 310 and the flash memory device 260 are coupled via respective device ports 350, 250 and communicate via communications link 300.
In different implementations, host device 310 sends to flash memory storage device 260 requests to read data stored in flash memory 270 and/or to write data to flash memory 270.
When data is written to flash memory 270 to a particular logical and/or physical location(s) within flash memory 270, one or more storage system data structure(s) (NOT SHOWN IN FIG. 2A) (for example, flash management tables) are updated to indicate that the logical and/or physical location within the flash is “occupied” or “full.” In the case of systems including multi-bit flash memory cells, the storage system data structure(s) may be updated to indicate how many bits are stored in a particular flash memory cell.
When data is erased from a particular logical and/or physical location within the flash, the one or more storage system data structure(s) (for example, flash management tables) are updated to indicate that the logical and/or physical location within the flash that was previously “occupied” or “full” is now “vacant” or “empty.” Thus, it is possible to determine the extent to which flash storage device is full of previously-written data by looking up this information in the storage system data structure(s).
Thus, any a given point in time, the storage system data structure(s) indicate “how full” flash device 260 (in particular flash memory 270) at the point in time.
There is no limitation on the location of the storage system data structure(s) (NOT SHOWN) and/or how the storage system data structure(s) are updated. In some implementations, the flash controller 280 and/or host device 310 are operative to update the storage system data structure(s) when data is written and/or erased to flash memory 270. In some implementations, the storage system data structure(s) reside in the flash memory 270 and/or elsewhere within the flash device 260. Alternatively or additionally, the storage system data structure(s) reside on the “host side.”
Multi-Die Flash Devices
Although flash memory 270 is illustrated as a single unit in FIG. 2A, it is appreciated by the skilled artisan that flash memory 270 may reside on a single die or may reside on multiple dies. FIG. 2B (prior art) is a block diagram of a multi-die flash memory 270 that includes N flash dies, where N is a positive integer. On each flash die resides a plurality of flash memory cells (not shown in FIG. 2B).